Nonvolatile memory device and method for fabricating the same

ABSTRACT

Disclosed is a nonvolatile memory device comprising a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second gate insulating layer and a control gate line deposited in one direction perpendicular to the first and second active regions and covering the floating gate; first impurity regions formed in the first and second active regions at one side of the control gate line; second impurity regions formed in the first and second active regions at other side of the control gate line; first contact plugs contacted with the first impurity regions; and a common conductive line formed in one direction on the semiconductor substrate at the other side of the control gate line, for connecting the second impurity regions of the first and second active regions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device and method for fabricating the same which is capable of reducing the size of a chip and simplifying the process for forming a common source line.

2. Background of the Related Art

In general, semiconductor memory devices are mainly divided into two main groups, i.e., a volatile memory device which is capable of erasing the stored data and then restoring new data, and a nonvolatile memory device which permanently reserves the stored data.

The volatile memory device includes a RAM capable of reading and writing of data and the nonvolatile memory device includes a ROM(Read Only Memory), EPROM(Erasable Programmable ROM) and EEPROM(Electrically Erasable Programmable ROM).

In the nonvolatile memory device, the ROM is not possible to reprogram once it stores the data. The EPROM and EEPROM is possible to erase the stored data and then reprogram. EPROM and EEPROM are the same in operation of programming the data, but different in methods of erasing the stored data. Specifically, the EPROM erases the stored data using ultraviolet and EEPROM erases the stored data electrically.

When a plurality of the nonvolatile memory devices are arranged in a form of matrix, sources of the nonvolatile memory devices can be connected for increasing the integration. Accordingly, methods for connecting sources of the nonvolatile memory devices have been studied.

With reference to the accompanying drawings, a related art nonvolatile memory device and a method for fabricating the same will be described.

FIG. 1 is a plan view showing a cell array of a related art nonvolatile memory device, FIG. 2a is sectional view showing a structure of the related art nonvolatile memory device taken along the line I—I in FIG. 1, and FIG. 2b is a sectional view showing a structure of the related art nonvolatile memory device taken along the line II—II in FIG. 1.

As shown in FIGS. 1, 2 a and 2 b, the related art nonvolatile memory device includes a semiconductor substrate 10 defining a plurality of active regions and a field region. A field oxide film 11 is formed on the field region. The active regions are aligned in one direction.

A plurality of tunneling oxide films 12 and floating gates 13 are deposited on each of the active regions in a predetermined pattern. Inter-poly dielectric layers 14 and control gate lines are deposited in a direction perpendicular to the active regions to cover the floating gates 13.

The control gate lines are formed to be bent outwardly, because an area for forming a contact wire in a common source ion injection region which is to be formed at a later step requires a greater margin.

The tunneling oxide films 12, floating gates 13, inter-poly dielectric layers 14 and control gate lines 15 are provided with sidewalls 19 a at both sides thereof. The sidewalls 19 a at the inner sides of the control gate lines 15 in which the common source ion injection region is to be formed are partially removed.

In a state that pairs each consisting of two, i.e., first and second control gate lines 15 are aligned, drain regions are formed in the semiconductor substrate 10 outside of the pairs of the first and second control gate lines 15. Also, a common source ion injection region 21 is formed in the semiconductor substrate 10 between the first and second control gate lines 15.

Referring to FIG. 1, the reference numerals 22 and 23 denote a drain wire and a source wire, respectively. The drain wire 22 is aligned with the active region to connect the drain regions on a same active region. The source wire 23 is aligned with the active region to connect the common source ion injection regions 21.

Referring to FIGS. 3a and 4 a, the process for manufacturing the above-explained related art nonvolatile memory device will be described.

A field oxide film 11 is formed on the field region of the semiconductor substrate 10 defining the active regions and the field region. A first oxide film and a first polysilicon layer are deposited in a direction aligned with each active region of the semiconductor substrate 10.

A second oxide film and a second polysilicon layer are successively deposited on the entire surface of the semiconductor substrate 10 using a chemical vapor deposition (CVD). A photo-sensitive film is coated on the second polysilicon layer and then patterned in one direction perpendicular to the active regions. The second polysilicon layer, the second oxide film, the first polysilicon layer and the first oxide film are successively anisotropic-etched, using the patterned photo-sensitive film as a mask.

By the above steps, as shown in FIGS. 3a and 4 a, the tunneling oxide film 12 and the floating gate 13 are formed on one portion of the active region of the semiconductor substrate 10 in a predetermined pattern. Also, an inter-poly dielectric layer 14 and a control gate line 15 are formed in one direction perpendicular to the active region to cover the floating gate 13. Then, the photo-sensitive film is removed.

Then, as shown in FIGS. 3b and 4 b, a first photo-sensitive film 16 is deposited on the entire surface of the semiconductor substrate 10. The first photo-sensitive film 16 is selectively patterned by exposing and developing process, so as to expose a portion of the active region of the semiconductor substrate 10 in which a drain region is to be formed.

First conductive ions are injected into the portion which is to be a drain region, using the patterned first photo-sensitive film as a mask, thereby forming a drain region 18.

By tilt ion injection method, second conductive ions are injected into a bottom portion of the floating gate 13 adjacent to the drain region, to form a halo ion region 17. Then, the first photo-sensitive film 16 is removed.

As shown in FIGS. 3c and 4 c, an insulating layer 19 is formed over the entire surface of the semiconductor substrate 10.

As shown in FIGS. 3d and 4 d, the insulating layer 19 is anisotropic-etched to form sidewalls 19 a at both sides of the tunneling oxide film 12, the floating gate 13, the inter-poly dielectric layer 14 and the control gate line 15.

As shown in FIGS. 3e and 4 e, a second photo-sensitive film 20 is coated on the entire surface of the semiconductor substrate 10. Then, the second photo-sensitive film 20 is selectively patterned by exposing and developing process, so as to expose the field oxide film 11 and the active regions between the control gate lines.

The field oxide film 11 and the sidewalls 19 a are anisotropic-etched to expose the semiconductor substrate 10 between the control gate lines 15 using the patterned second photo-sensitive film 20 as a mask. At this time, there occurs a problem that the surface of the active region of the semiconductor substrate 10 is etched.

The process for etching the field oxide film 11 using the second photo-sensitive film 20 and sidewall 19 a as a mask in order to form a common source ion injection region is referred to as a self-align source dry-etching process.

The first conductive ions are injected into the exposed portion of the semiconductor substrate 10 between the control gate lines 15 to form a common source ion injection region 21 in one direction between the control gate lines 15.

However, the related art nonvolatile memory device and the method for fabricating the same has the following problems.

First, when the field oxide film is removed, i.e., when the self-align source dry-etching process is performed in order to form a common source ion injection region, the semiconductor substrate may be lost to reduce the reliance on the operation of the semiconductor device.

Second, if ions are injected into the lost portion of the semiconductor substrate after the self-align source dry-etching process, it is not easy to control the concentration of the source region.

Third, the sidewalls of the active regions are lost during the self-align source dry-etching process, thus, the control gate lines and the inter-poly dielectric layer may be damaged.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.

Another object of the present invention is to provide a nonvolatile memory device and a method for fabricating the same which is capable of increasing the integration of a semiconductor device, simplifying the process for forming a common source line and improving the reliance on the operation of the device.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.

To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a nonvolatile memory device includes a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second gate insulating layer and a control gate line deposited in one direction perpendicular to the first and second active regions and covering the floating gate; first impurity regions formed in the first and second active regions at one side of the control gate line; second impurity regions formed in the first and second active regions at other side of the control gate line; first contact plugs contacted with the first impurity regions; and a common conductive line formed in one direction on the semiconductor substrate at the other side of the control gate line, for connecting the second impurity regions of the first and second active regions.

A method for fabricating a nonvolatile memory device according to the invention includes the steps of defining first and second active regions to be arranged on a semiconductor substrate in one direction; depositing a first gate insulating layer and a floating gate on the first and second active regions in a predetermined pattern, and depositing a second gate insulating layer and a control gate line in one direction perpendicular to the first and second active regions to cover the floating gate; forming first impurity regions in the first and second active regions at one side of the control gate line; forming second impurity regions in the first and second active regions at other side of the control gate line; forming a buffer insulating layer on the entire surface of the semiconductor substrate including the first and second impurity regions; forming a first interlayer dielectric on the semiconductor substrate such that first contact holes are provided in the first impurity regions and that a line-type contact hole is formed by connecting and exposing the second impurity regions of the first and second active regions; forming a third impurity region by injecting ions into the first and second impurity regions exposed by the first contact holes and the line-type contact hole; removing the buffer insulating layer from the first contact holes and the line-type contact hole; and forming first contact plugs in the first contact holes and forming a common conductive line in the line-type contact hole.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

FIG. 1 is a plan view showing a cell array of a related art nonvolatile memory device;

FIG. 2a is a sectional view showing a structure of the related art nonvolatile memory device taken along the line I—I in FIG. 1;

FIG. 2b is a sectional view showing a structure of the related art nonvolatile memory device taken along the line II—II in FIG. 1;

FIGS. 3a to 3 f are sectional views showing the process for forming the related art nonvolatile memory device taken along the line I—I in FIG. 1;

FIGS. 4a to 4 f are sectional views showing the process for forming the related art nonvolatile memory device taken along the line II—Il in FIG. 1;

FIG. 5 is a plan view showing a cell array of a nonvolatile memory device in accordance with the present invention;

FIG. 6a is a sectional view showing a structure of the invented nonvolatile memory device taken along the line III—III in FIG. 5;

FIG. 6b is a sectional view showing a structure of the invented nonvolatile memory device taken along the line IV—IV in FIG. 5;

FIG. 6c is a sectional view showing a structure of the invented nonvolatile memory device taken along the line V—V in FIG. 5;

FIGS. 7a to 7 i are sectional views showing the process for forming the invented nonvolatile memory device taken along the line III—III in FIG. 5; and

FIGS. 8a to 8 i are sectional views showing the process for forming the invented nonvolatile memory device taken along the line IV—IV in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

FIG. 5 is a plan view showing a cell array of a nonvolatile memory device in accordance with the present invention. FIG. 6a is a sectional view showing a structure of the invented nonvolatile memory device taken along the line III—III in FIG. 5, FIG. 6b is a sectional view showing a structure of the invented nonvolatile memory device taken along the line IV—IV in FIG. 5, and FIG. 6c is a sectional view showing a structure of the invented nonvolatile memory device taken along the line V—V in FIG. 5.

Referring to FIGS. 5 and 6a to 6 c, a nonvolatile memory device of the present invention includes a semiconductor substrate 30 defining active regions and field region. A field oxide film 31 is formed on the field region. The plurality of active regions are aligned in one direction.

A plurality of tunneling oxide films 32 and floating gates 33 are deposited on the active regions in a predetermined pattern. A plurality of inter-poly dielectric layers 34, control gate lines 35 and cap insulating layers 36 are deposited on the field oxide film 31 and the floating gates 33 in one direction perpendicular to the active regions.

A plurality of sidewalls 42 a are formed at both sides of the tunneling oxide film 32, floating gate 33, inter-poly dielectric layer 34, control gate line 35 and cap insulating layer 36. A buffer nitride layer 43 is deposited on the cap insulating layer 36 at a thickness of 50-500 Å.

The control gate lines 35 are formed as a plurality of pairs each consisting of two, i.e., first and second control gate lines. The pair of control gate lines 35 lines will be explained below.

Drain regions are formed in the active regions outside a pair consisting of first and second control gate lines 35, and source regions are formed in the active regions between the first and second control gate lines 35.

Each of the drain regions includes a low concentration drain region 39 and a high concentration drain region 46 a. The low concentration drain region 39 is formed in the semiconductor substrate 30 outside the pair of the first and second control gate lines 35 and under the sidewalls 42 a. The high concentration drain region 46 a is formed deeper than the low concentration drain region 39 and extended into a low portion of the semiconductor substrate 30 under the tunneling oxide film 32.

Low concentration halo ion regions 38 are formed at both sides of the low concentration drain region 39.

Each of the source regions includes a low concentration source region 41 and a high concentration source region 46 b. The low concentration source region 41 is formed in the semiconductor substrate 30 between the first and second control gate lines 35. The high concentration source region 46 b is formed deeper than the low concentration source region 41 and extended into a low portion of the semiconductor substrate 30 under the tunneling oxide film 32.

A first interlayer dielectric 44 is formed such that first contact holes are provided in each of the low concentration drain region 39 and that line-type contact holes are provided in one direction perpendicular to the active regions so as to expose the field oxide film 31 and the active regions (source regions) between the first and second control gate lines.

The first contact holes and line-type contact holes are formed by a self-align contact process using the sidewall 42 a and the buffer nitride layer 43.

Tungsten plugs 47 a are provided for burying each of the first contact holes and line-type contact holes of the first interlayer dielectric 44.

The tungsten plug 47 a formed on the semiconductor substrate 30 (source regions and field oxide film 31) for connecting the low concentration source regions 41 between the first and second control gate lines is referred to as a common source line.

A second interlayer dielectric 48 is formed such that second contact holes are provided in the tungsten plugs 47 a on the low concentration drain regions 39 in the first active region and that a third contact hole is provided in one portion of the common source line between the first and second control gate lines 35 in the second active region.

The second contact holes are provided with contact plugs 49 a, and the third contact hole is provided with a contact plug 49 b. Drain wires 50 a are formed on the second interlayer dielectric 48 and on the contact plugs 49 a in the second contact holes formed on a same active region, to be aligned with the active region. Source wires 50 b are formed on the second interlayer dielectric 48 and on the contact plug 49 b of the third contact hole, to be aligned with the active region. The drain wires 50 a and the source wires 50 b are formed on different active regions.

The above-explained nonvolatile memory device consists of two active regions; tunneling oxide film 32 and floating gate 33 deposited on the active regions in a predetermined pattern; inter-poly dielectric layer 34 and control gate line 35 deposited in a direction perpendicular to the active regions to cover the floating gate 33 of the active regions; drain regions formed in the active region at one side of the control gate line 35; source regions formed in the active region at the other side of the control gate line 35; and tungsten plugs 47 a arranged in one direction at the other side of the control gate line 35 for connecting the source regions of the active region, and formed in the drain regions.

The tungsten plug 47 a connecting the source regions in one direction is referred to as a common source line.

Fabricating method a nonvolatile memory device according to a preferred embodiment of the present invention will be described with reference to the attached drawings.

FIGS. 7a to 7 i are sectional views showing the process for forming the invented nonvolatile memory device taken along the line III—III in FIG. 5. FIGS. 8a to 8 i are sectional views showing the process for forming the invented nonvolatile memory device taken along the line IV—IV in FIG. 5.

Referring to FIGS. 7a and 8 a, a field oxide film 31 is formed on the field region of the semiconductor substrate 30 defining a plurality of active regions and the field region. The active regions are arranged in one direction.

Then, although not shown in the Figures, using heat oxidation or chemical vapor deposition (CVD), a first oxide film is formed on the entire surface of the semiconductor substrate 30, and a first polysilicon layer is deposited on the first oxide film. A photo-sensitive film is coated on the first polysilicon layer, and then patterned to be parallel to and in line with the active regions. The first polysilicon layer and the first oxide film are successively anisotropic-etched using the patterned photo-sensitive film as a mask, to arrange the first polysilicon layer and the first oxide film in one line. Then, the photo-sensitive film is removed.

Also, although not shown in the Figures, a second oxide film, a second polysilicon layer and an oxide film(or nitride film) are successively deposited on the entire surface of the semiconductor substrate 30 using CVD. A photo-sensitive film is coated on the second polysilicon layer, and then patterned in one direction perpendicular to the active regions. The second polysilicon layer, the second oxide film, the first polysilicon layer and the first oxide film are successively anisotropic-etched, using the patterned photo-sensitive film as a mask.

By using the above-explained steps, a plurality of tunneling oxide films 32 and floating gates 33 are deposited on one portion of the active regions of the semiconductor substrate 30 in a predetermined pattern. A plurality of inter-poly dielectric layers 34, control gate lines 35 and cap insulating layers 36 are deposited in one direction perpendicular to the active regions to cover the floating gate 33. Then, the photo-sensitive film is removed.

Two, i.e., first and second control gate lines 35 forms a pair. The first and second control gate lines 35 share a source.

As shown in FIGS. 7b and 8 b, the entire surface of the semiconductor substrate 30 is coated with a first photo-sensitive film 37. Then, the photo-sensitive film 37 is selectively patterned by exposing and developing process, so as to expose a portion of the active regions in the semiconductor substrate 30 in which drain regions are to be formed.

First conductive ions of low concentration are injected into the drain region of the semiconductor substrate 30, using the patterned first photo-sensitive film 37 as a mask, to form a low concentration drain region 39. By tilt ion injection method, second conductive ions are injected into one portion at the bottom of the floating gate 33 adjacent to the drain region to form a halo ion region 38. Then, the first photo-sensitive film 37 is removed.

Phosphorus and boron ions are used as the first and second conductive ions, respectively, and each are injected at a concentration of 1E¹²-1E¹⁴. The second conductive ions are injected at an angle of 30-60 degrees.

As shown in FIGS. 7c and 8 c, the entire surface of the semiconductor substrate 30 is coated with a second photo-sensitive film 40. Then, the second photo-sensitive film 40 is selectively patterned by using exposing and developing process, so as to expose a portion of the active region in the semiconductor substrate 30 in which a source region is to be formed.

A first conductive ions of low concentration are injected into the source region in the semiconductor substrate 30, using the patterned second photo-sensitive film 40 as a mask, to form a low concentration source region 41. Then, the second photo-sensitive film 40 is removed.

Phosphorus ions are used as the first conductive ions and injected at a concentration of 1E¹²˜1E¹⁵.

Referring to FIGS. 7d and 8 d, an insulating layer 42 of oxide or nitride is deposited on the entire surface of the semiconductor substrate 30 using CVD. The deposited insulating layer 42 has a thickness of 1000-3000 Å.

As shown in FIGS. 7e and 8 e, the insulating layer 42 is anisotropic-etched to form sidewalls 42 a at both sides of the tunneling oxide film 32, the floating gate 33, the inter-poly dielectric layer 34, the control gate line 35 and the cap insulating layer 36.

A buffer nitride film 43 of a thin thickness is deposited on the entire surface of the semiconductor substrate 30 including the low concentration source/drain regions 41 and 39, sidewalls 42 a and cap insulating layer 36. The deposited buffer nitride film 43 has a thickness of 50-500 Å.

Referring to FIGS. 7f and 8 f, a first interlayer dielectric 44 is deposited on the entire surface of the buffer nitride film 43 to have a thickness of 5000-10,000 Å.

Then, chemical and mechanical polishing process, or etch-back process is used to flatten the first interlayer dielectric 44.

A third photo-sensitive film 45 is coated on the first interlayer dielectric 44 and selectively patterned by using exposing and developing process to expose the source and drain regions of the active regions.

The first interlayer dielectric 44 is anisotropic-etched using the patterned third photosensitive film 45 as a mask to form a first contact hole and a line-type contact hole in the drain and source regions, respectively.

In the formation of the line-type contact hole, the first interlayer dielectric 44 is removed so as to expose the field oxide film 31 and the low concentration source region 41 between the first and second control gate lines 35.

A high concentration drain region 46 a and a high concentration source region 46 b are formed by injecting first conductive ions of high concentration into the low concentration source/drain region 41 and 39 exposed by using the third photo-sensitive film 45 and the first interlayer dielectric 44.

As the first conductive ions, arsenic ions (As+) are injected at a concentration of 1E 4 -5E 5 and at an angle of 30-60 degrees. Then, the third photo-sensitive film 45 is removed.

When forming the first contact hole and the line-type contact hole in the drain and source regions using the third photo-sensitive film 45, the buffer nitride film 43 acts as an etching stopper, which is referred to as a self-align contact process. Using the buffer nitride film 43 as an etching stopper prevents damage on the semiconductor substrate 30 in the contact process.

The buffer nitride film 43 may be removed after the formation of the first contact hole and the line-type contact hole in the drain and source regions, or after the formation of the high concentration drain region 46 a and the high concentration source region 46 b.

As shown in FIGS. 7g and 8 g, a tungsten layer 47 is deposited on the entire surface of the semiconductor substrate 30 including the first contact hole and the line-type contact hole. The deposited tungsten layer 47 has a thickness of 5000-10,000 Å.

Referring to FIGS. 7h and 8 h, the tungsten layer 47 is removed using chemical and mechanical polishing process or etch-back process until the first interlayer dielectric 44 is exposed, thereby forming tungsten plugs 47 a in the first contact hole of the drain region and in the line-type contact hole of the source region.

The tungsten plugs 47 a in the drain region are separated from each other. The tungsten plugs 47 a in the source region are formed in one direction between the first and second control gate lines so as to connect the source regions of each active region between the first and second control gate lines. This is referred to as a common source line.

Referring to FIG. 7i, a second interlayer dielectric 48 is deposited on the tungsten plugs 47 a and the first interlayer dielectric 44, and then anisotropic-etched to form second contact holes in the tungsten plugs 47 a contacted with the drain region of the active regions and to form a third contact hole in the tungsten plugs 47 a (i.e., the common source line) arranged in one direction in the source region of the active regions. The second contact holes and the third contact hole are formed on different portions of the active regions.

After contact plugs 49 a and 49 b are formed in the second and third contact hole, respectively, drain wires 50 a are formed on the second interlayer dielectric 48 in parallel to the active regions, for connecting the contact plugs 49 a formed in the drain region on a same active region.

Simultaneously with the formation of the drain wires 50 a, source wires 50 b are formed on the second interlayer dielectric 48 to be contacted with one portion of the contact plug 49 b of the source region and to be arranged parallel to the active region.

The drain and source wires 50 a and 50 b are formed on different portions of the active regions.

As described, the nonvolatile memory device and the method for fabricating the same in accordance with the present invention has the following advantages.

First, since self-align contact process is used for forming a common source line, in application of a same deign rule, the size of unit cell of the nonvolatile memory device can be reduced by 70% compared with the related art device. Accordingly, integration of the device can be realized.

Second, by using a buffer nitride oxide film as an etching stopper during the self-align contact process, damage on the semiconductor substrate can be prevented. Accordingly, current leakage is suppressed and reliability on the operation of the device is improved.

Third, by using chemical and mechanical polishing, or etching back process for forming a common source line, i.e., tungsten plugs on the semiconductor substrate in one direction, self-align source dry-etching process for etching a field oxide film between the source regions is not necessary. Thus, simplification of the fabricating process is attained.

The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. 

What is claimed is:
 1. A method for fabricating a nonvolatile memory device comprising the steps of: defining first and second active regions to be arranged on a semiconductor substrate in one direction; depositing a first gate insulating layer and a floating gate on the first and second active regions in a pattern, and depositing a second gate insulating layer and a control gate line in one direction perpendicular to the first and second active regions to cover the floating gate; forming first impurity regions in the first and second active regions at one side of the control gate line; forming second impurity regions in the first and second active regions at other side of the control gate line; forming a buffer insulating layer on the entire surface of the semiconductor substrate including the first and second impurity regions; forming a first interlayer dielectric on the semiconductor substrate such that first contact holes are provided in the first impurity regions and that a line-type contact hole is formed by connecting and exposing the second impurity regions of the first and second active regions; forming a third impurity region by injecting ions into the first and second impurity regions exposed by the first contact holes and the line-type contact hole; removing the buffer insulating layer from the first contact holes and the line-type contact hole; and forming first contact plugs in the first contact holes and forming a common conductive line in the line-type contact hole.
 2. The method as claimed in claim 1, wherein the buffer insulating layer is formed of nitride film.
 3. The method as claimed in claim 1, wherein the buffer insulating layer has a thickness within the range of 50-500 Å.
 4. The method as claimed in claim 1, wherein the first contact plugs and the common conductive line are formed through steps of depositing a tungsten layer on the first interlayer dielectric provided with the first contact holes and the line-type contact hole, and etching back or chemically and mechanically polishing the tungsten layer.
 5. The method as claimed in claim 1, further comprising the steps of: forming a second interlayer dielectric layer such that second contact holes are provided on the first contact plugs and that a third contact hole is provided in one portion of the common conductive line; forming second contact plugs in the second contact holes, and simultaneously, forming third contact plugs in the third contact hole; and forming first wires in one direction on the second contact plugs and the second interlayer dielectric for connecting the second contact plugs, and simultaneously, forming a second wire in one direction on the second interlayer dielectric to be contacted with the third contact plug.
 6. The method as claimed in claim 1, wherein phosphorus ions are injected into the first impurity regions at a concentration of 1E¹²-1E¹⁴.
 7. The method as claimed in claim 1, wherein a halo ion injection region is additionally formed in one portion of the first impurity regions in the semiconductor substrate.
 8. The method as claimed in claim 7, wherein boron ions are injected into the halo ion injection regions at a concentration of 1E¹²-1E¹⁴.
 9. The method as claimed in claim 7, wherein the halo ion injection regions are formed by injecting ions at an angle of 30-60 degrees.
 10. The method as claimed in claim 1, wherein phosphor ions are injected into the second impurity regions at a concentration of 1E¹²-1E¹⁵.
 11. The method as claimed in claim 1, wherein a cap insulating layer is additionally formed on the control gate line.
 12. The method as claimed in claim 1, wherein arsenic ions (As+) are injected into the third impurity region at a concentration of 1E¹⁴-1E¹⁵ and at an angle of 30-60 degrees.
 13. A method for fabricating a nonvolatile memory device comprising the steps of: defining a plurality of active regions to be arranged on a semiconductor substrate in one direction; depositing a plurality of first gate insulating layers and floating gates on the active regions in a pattern, and depositing a plurality of pairs each consisting of two second gate insulating layers and a plurality of pairs each consisting of first and second control gate lines in one direction perpendicular to the active regions to cover the floating gates; forming first impurity regions in the active regions outside the pair of the first and second control gate lines; forming second impurity regions in the active regions between the first and second control gate lines; forming a buffer insulating layer on the entire surface of the semiconductor substrate including first and second impurity regions; forming a first interlayer dielectric on the semiconductor substrate such that first contact holes are provided in the first impurity regions and that line-type contact holes are formed by connecting and exposing the second impurity regions between the first and second control gate lines; forming a third impurity region by injecting ions into the first and second impurity regions exposed by the first contact holes and the line-type contact holes; removing the buffer insulating layer from the first contact holes and the line-type contact holes; and forming first contact plugs in the first contact holes and forming common conductive lines in the line-type contact holes between the first and second control gate lines.
 14. The method as claimed in claim 13, wherein the buffer insulating layer is formed of nitride film.
 15. The method as claimed in claim 13, wherein the buffer insulating layer has a thickness within the range of 50-500 Å.
 16. The method as claimed in claim 13, wherein the first contact plugs and the common conductive lines are formed through steps of depositing a tungsten layer on the first interlayer dielectric provided with the first contact holes and the line-type contact holes, and etching back or chemically and mechanically polishing the tungsten layer.
 17. The method as claimed in claim 13, further comprising the steps of: forming a second interlayer dielectric layer such that second contact holes are provided on the first contact plugs and that third contact holes are provided in one portion of the common conductive lines; forming second contact plugs in the second contact holes, and simultaneously, forming third contact plugs in the third contact holes; and forming a plurality of first wires in one direction on the second contact plugs and the second interlayer dielectric for connecting the second contact plugs formed on a same active region, and simultaneously, forming a plurality of second wires in one direction on the second interlayer dielectric to be contacted with the third contact plugs.
 18. The method as claimed in claim 13, wherein phosphorus ions are injected into the first impurity regions at a concentration of 1E¹²-1E¹⁴.
 19. The method as claimed in claim 13, wherein a halo ion injection region is additionally formed in one portion of the first impurity regions in the semiconductor substrate.
 20. The method as claimed in claim 19, wherein boron ions are injected into the halo ion injection region at a concentration of 1E¹²-1E¹⁴.
 21. The method as claimed in claim 19, wherein the halo ion injection region is formed by injecting ions at an angle of 30-60 degrees.
 22. The method as claimed in claim 13, wherein phosphorus ions are injected into the second impurity regions at a concentration of 1E¹²-1E¹⁵.
 23. The method as claimed in claim 13, wherein a cap insulating layer is additionally formed on the control gate lines.
 24. The method as claimed in claim 13, wherein arsenic ions (As+) are injected into the third impurity region at a concentration of 1E¹⁴-1E¹⁵ and at an angle of 30-60 degrees. 